Module name: src
Changes by: miod@cvs.openbsd.org 2014/08/18 11:23:06

Modified files:
sys/arch/mips64/mips64: trap.c

Log message:
Sigh, ignoring instruction fetch bus errors for the kernel code should not
depend upon the address being at the beginning of a cache line, for we may
arrive in the middle of a line thanks to a branch. Noticed the hard way...